1. Field of the Invention
The present invention generally relates to a semiconductor package structure and a manufacturing process thereof, and more particularly, to a semiconductor package structure with through silicon vias (TSVs) and a manufacturing process thereof.
2. Description of Related Art
In a semiconductor packaging process, through silicon vias (TSVs) are formed to electrically connect dies and wafers vertically. The TSV technique is very important in connecting dies in 3-dimensional (3D) integrated circuits (IC). Compared to the conventional IC packaging techniques, the TSV technique offers a maximum 3D density, a smaller size, a higher speed, a reduced signal delay, and a lower power consumption. Thus, the TSV structure is considered a new-generation vertical interconnect structure applied to 3D IC technology.
To be specific, in a semiconductor packaging process, a semiconductor wafer is first thinned to expose the TSVs in a semiconductor wafer. The semiconductor wafer is then temporarily fixed on a carrier wafer. Next, uncut dies are bonded to the semiconductor wafer. After that, the semiconductor wafer is separated from the carrier wafer in order to perform subsequent processes on the semiconductor wafer. However, when the semiconductor wafer and the carrier wafer are separated, the semiconductor wafer may be deformed due to variation of structural stress. As a result, the production yield may be reduced.